The present invention relates to a bus control system, and more particularly to a bus control system capable of high speed processing, priority processing and interrupt processing of bus data.
It has been known to connect a data processing unit, memory units and input and/or output (I/O) devices through buses and transfer addresses and data among those units and devices through the buses for data processing. The buses for transferring the address signals and the data signals are referred to as an address bus and a data bus, respectively.
A control system for those buses is well known by, for example, the guide book entitled "8289 Bus Arbiter" published by Intel Corp. in Feburary 1979.
In the known bus control system, when a single bus is shared by a plurality of I/O devices, the I/O devices, may content for the use of the bus. In order to resolve the contention, a polling system (scan system) and a contention system (interrupt system) have been used.
In the polling system, acknowledgement for sending is given from the data processing unit to the I/O devices sequentially in the order of priority. When a large number of I/O devices are connected, a time interval for the respective I/O devices to receive the acknowledgement for sending increases and hence a waiting time of the respective I/O device increases. In addition, since the same acknowledgement signal is repeatedly sent irrespective of the sending frequency of each of the I/O devices, the efficiency of bus utilization is low.
In this system, while one I/O device is continuously using the bus, a higher priority I/O device cannot interrupt even if it requests to use the bus.
In the contention system, the data processing unit does not control the I/O devices but the respective I/O device sends a request-to-send signal to inform the bus request to other I/O devices before it sends out a signal on the bus. In this system, the data processing unit has the same order of priority as the I/O devices. When more than one I/O device issues the request-to-send signals simultaneously, the I/O device of the highest priority is given right to use the bus.
In this system, even when one I/O device wishes to continue the use of the bus, other I/O devices may interrupt and the sending of a command by the first I/O device will be disconnected.
Furthermore, in the prior art system, when a high speed processing unit, such as a hardware operation unit, is operated at a high speed, continuous operation thereof is interrupted because a memory request is issued from another device every time a memory request is completed. Accordingly, a desired high speed operation is not attained. If the hardware operation unit is allowed to issue memory requests sequentially in order to attain the high speed operation, the data transfer from another device to the memory unit is inhibited or interrupted which can not otherwise be accepted at an end of block of commands.